The field of the invention is the use of cache memory, and in particular directory lookups in cache memories.
Cache memories have long served to make computers more efficient, by providing a relatively small and relatively fast local storage in a processing device. The cache allows currently active data to be accessed conveniently by an associated processor without accesses to the relatively larger and slower main memory—or worse still, the even larger and slower disk. In multi-processor systems with speculative execution, caching has become quite elaborate. The prior generation of IBM® Blue Gene® supercomputer system had three levels of caches, denoted L1, L2, and L3.
One common technique for organizing a cache is to make it set associative. This means that the cache is organized into pieces. Each piece is called a set. Each set includes a number of ways, each including a cache line. A memory access request accesses a set stored in a cache directory, and selects a way and thus a line of the cache.
For more information on caches, the reader is directed to the article entitled “CPU Cache” in Wikipedia.
Due to the requirements of such systems, and due to the decreasing cost of memory, caches have become much larger and more numerous. In a supercomputer, there may be thousands of cache memories each having more than 10 MB of data. These supercomputers can draw electrical power on the order of megawatts. Each component must be scrutinized for possible energy efficiency improvement